02-17-2025, 05:35 PM
(This post was last modified: 02-17-2025, 08:38 PM by physics.
Edit Reason: Clarification.
)
Thanks for the info Kevin!
Edit: Kevin pointed out the circuit description that follows is confusing. It was meant to describe one of the DC-coupled PPIMV's in TUT4, not the F/S PPIMV. I'm leaving the description as-is to not mess with history/remove context for post #4.
The F/S PPIMV looks similar to the design you put in TUT4, with pot wiper to top of grid leak, the bottom of the pot to -Vb, and the top of the pot to the PI coupling cap. That one reduces the grid-leak to zero as well, but it keeps a relatively high impedance shown to the PI. It also has actual voltage-divider action happening with the pot instead of loading down the PI, if I understand it correctly. Would there be any reason to prefer the TUT4 implementation over the F/S implementation?
Thanks,
physics
Edit: Kevin pointed out the circuit description that follows is confusing. It was meant to describe one of the DC-coupled PPIMV's in TUT4, not the F/S PPIMV. I'm leaving the description as-is to not mess with history/remove context for post #4.
The F/S PPIMV looks similar to the design you put in TUT4, with pot wiper to top of grid leak, the bottom of the pot to -Vb, and the top of the pot to the PI coupling cap. That one reduces the grid-leak to zero as well, but it keeps a relatively high impedance shown to the PI. It also has actual voltage-divider action happening with the pot instead of loading down the PI, if I understand it correctly. Would there be any reason to prefer the TUT4 implementation over the F/S implementation?
Thanks,
physics


